1. Field of the Invention
This invention relates to high speed data processing in particular to a high speed parallel backplane for interconnecting a plurality of printed circuit boards in a parallel processing system.
2. Description of the Prior Art
The conventional approach to parallel backplane design utilizes a set of circuit board connectors mounted on a flat supporting structure typically made of phenolic glass-epoxy. Common bus pins are interconnected via a set of linear metallized traces deposited on the supporting structure. Although this technique is acceptable for systems supporting low bandwidth applications, it begins to fail as the bus bandwidth exceeds 15 MHz. Of all the physical parameters which affect bus bandwidth, signal path length is the most crucial. According to the law of electromagnetics, when a signal path length approaches a quarter wavelength of operating frequency, radiative losses occur. This not only distorts the waveform present on the signal path, but also increases coupling between adjacent signal path elements, such as the linear traces on a conventional backplane. Thus, as the bus bandwidth increases, the linear parallel traces become inductively coupled and even begin to act as radiating elements thereby introducing cross-talk.
Current bus designs use a variety of mechanical shielding approaches and electrical termination schemes in an attempt to rectify the problem, but small changes in operating frequency and/or number of supported interconnects can often change the characteristic impedance of the system. Other conventional designs try to prevent the quarter wavelength effect by alternating signal and ground paths to shield the adjacent signal lines from one another. While these and other approaches have met with limited success, they all leave the basic problem of the quarter wavelength limit unsolved.